Sr. Analog IC Design Engineer

Job Title: Analog Mixed-Signal Design Engineer

Location: Bay Area, CA

Employment Type: Contract

Job Description

We are seeking an experienced Analog/Mixed-Signal Design Engineer to support the development of advanced semiconductor products using leading-edge 2nm/3nm CMOS process technologies . The ideal candidate will have strong hands-on experience designing, simulating, verifying, and optimizing transistor-level analog and mixed-signal circuits in advanced technology nodes.

The engineer will work closely with analog, digital, layout, verification, and physical design teams to develop high-performance, low-power, and robust circuit solutions and ensure successful implementation from schematic through post-layout verification.

Responsibilities

• Design and develop analog and mixed-signal circuits at the transistor level using advanced 2nm/3nm CMOS technologies .
• Perform schematic capture, circuit simulation, analysis, and optimization.
• Develop and verify circuits across PVT corners, Monte Carlo variation, mismatch, aging, and reliability conditions .
• Perform DC, AC, transient, noise, stability, and other circuit-level analyses as required.
• Work closely with layout engineers to guide layout implementation and ensure proper analog layout techniques.
• Review layouts for matching, symmetry, shielding, parasitic sensitivity, noise coupling, and signal integrity.
• Perform parasitic extraction and post-layout simulation to validate circuit performance.
• Debug discrepancies between schematic-level and extracted-layout simulations.
• Optimize circuit performance for power, performance, area, noise, linearity, and robustness.
• Participate in design reviews and provide technical recommendations throughout the design cycle.
• Support design integration, verification, tapeout, and silicon bring-up as required.
• Collaborate with digital, verification, physical design, process, and modeling teams to resolve cross-functional design issues.
• Document design assumptions, simulation results, tradeoffs, and verification results.

Required Qualifications

• Strong hands-on experience in analog and mixed-signal IC design .
• Demonstrated experience designing transistor-level circuits in 2nm and/or 3nm CMOS process technologies .
• Strong understanding of CMOS device behavior, process variation, mismatch, parasitics, and advanced-node design considerations.
• Experience with transistor-level circuit design, simulation, debugging, and verification.
• Proficiency with Cadence Virtuoso schematic and layout environments.
• Strong experience with Cadence Spectre/Spectre X or equivalent SPICE-level simulation tools.
• Hands-on experience with analog layout methodologies and layout-dependent effects.
• Experience with parasitic extraction and post-layout verification .
• Strong understanding of PVT analysis, Monte Carlo simulation, device mismatch, and statistical variation.
• Ability to analyze and optimize circuits for power, performance, area, noise, and reliability.
• Strong debugging and problem-solving skills.
• Ability to work effectively with cross-functional engineering teams.

Preferred Experience

Experience in one or more of the following areas is highly desirable:

• PLLs, DLLs, clocking circuits, or oscillators
• ADCs/DACs and data converters
• SerDes or high-speed I/O
• Voltage regulators, LDOs, and power-management circuits
• Bandgaps, references, and bias-generation circuits
• Amplifiers, comparators, and analog front ends
• Memory-related analog circuits
• High-speed clock and data paths
• Mixed-signal interfaces between analog and digital domains
• FinFET/GAA device architectures and associated advanced-node design challenges
• Reliability analysis, EM/IR considerations, aging analysis, and advanced-node signoff

Education / Experience

• BS or MS in Electrical Engineering, Microelectronics, or a related field.
• Typically 7+ years of relevant analog/mixed-signal IC design experience , with significant recent hands-on design experience preferred.
• Prior successful tapeout experience in advanced CMOS technology nodes is strongly preferred.

Ideal Candidate

The ideal candidate is a highly hands-on circuit designer who can take ownership of a block from architecture and transistor-level design through schematic verification, layout interaction, extraction, post-layout verification, and tapeout readiness . Experience working directly with leading-edge foundry processes, particularly 2nm/3nm , is a key requirement for this position.

Rate Range:

$80/hour - $160/hour