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Sr Digital Design Engineer

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Onsite

Sr Digital Design Engineer

Analog Devices

Sr Digital Design Engineer

Skills

Python

1 month ago

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Important information


Contract type:

Permanent

Location:

Hyderabad, Telangana, India

Work mode:

Onsite

Published on:

25 September 2026

What they need


Job Summary

Analog Devices, Inc. are looking for an experienced Digital Design Engineer to join our Automotive Networking team in Hyderabad, India. As a Senior Digital Design Engineer, you will lead block-level designs and verification efforts. You'll be responsible for complex digital subsystems, timing closure, and power optimization while mentoring junior engineers. This position requires deep understanding of digital design methodologies and the ability to interact with customers to gather requirements and provide technical solutions.

Key Responsibilities

  • Collaborate with cross-functional teams to help define requirements, architecture, and design specifications

  • Architect, design, implement, and maintain RTL IP for Digital systems

  • Design optimization with respect to performance, power, and area (PPA)

  • Run and support simulation, synthesis, and timing analysis for RTL IP

  • Work closely with verification engineers to define test strategies and support debug

  • Participate in design and architecture reviews, contributing to technical discussions and trade off decisions

  • Contribute to methodology improvements and best practices across the organization

    What We're Looking For

We're looking for engineers with solid digital design fundamentals who enjoy working on innovative products and collaborating across teams. The ideal candidate would match the criteria listed below.

Minimum Requirements

  • Bachelor's/Master's degree in Electronic Engineering or a related field.

  • Minimum of 6 years experience in digital design or related field

    Core experience (important for the role)

  • Proven track record of block-level design and verification for complex digital systems (with Verilog/SystemVerilog)

  • Proven track record for design closure activities including timing closure, power optimization, and area optimization

  • Familiarity with a requirements driven design flow

  • Programming experience in one or more languages (eg C/C++, Python, TCL)

  • Experience designing and integrating multi-clock digital systems

  • Experience with common on chip communication protocols such as SPI, I2C, or UART

    Experience that's a plus, but not essential

  • FPGA emulation or pre-silicon system validation experience

  • Exposure to Ethernet, switching, packet processing, TSN, or related networking technologies

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

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