Sr. Digital RTL Engineer

The Role

We're looking for a Senior Digital RTL Engineer to own digital control, beamforming, and interface logic at the heart of our phased-array solutions. As one of our early senior digital hires, you will not just execute against a spec—you will contribute to architecture and design methodology, take blocks from concept through silicon or FPGA bring-up, and help shape how the team works as it grows.

You'll own digital RTL design from architecture through synthesis, timing closure, and silicon/FPGA validation, working closely with RFIC, antenna, and DSP teams. The decisions you make will ripple through every product we build.

Responsibilities

• Design and implement production-quality digital RTL (SystemVerilog/Verilog) for beamformer control, phase/amplitude control interfaces, calibration logic, high-speed data paths, and system-level digital blocks
• Drive designs from specification and architecture definition through RTL coding, synthesis, timing analysis, place-and-route support, and silicon/FPGA validation
• Perform functional simulation, lint, CDC analysis, and timing closure; collaborate on verification planning and coverage for your blocks
• Work with RFIC, antenna, and DSP teams to define digital interfaces, control protocols, and system-level requirements
• Support lab bring-up, debug, and design iteration of fabricated ASICs or FPGA-based prototypes
• Improve RTL coding standards, review designs from peers, and mentor more junior engineers as the team grows
• Contribute to technical strategy, design reviews, documentation, and the digital design methodology

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
• 7–10 years of relevant experience in digital RTL design for ASICs or FPGAs
• Strong proficiency in SystemVerilog/Verilog and industry-standard tools (e.g., Cadence/Synopsys synthesis and STA, simulation environments, lint/CDC tools)
• Solid command of digital design fundamentals: synchronous design, timing closure, clock-domain crossing, finite-state machines, and high-speed interfaces
• Proven experience taking designs through synthesis, timing closure, and post-silicon or FPGA validation
• Demonstrated ability to own non-trivial blocks end-to-end and work across RFIC, DSP, and implementation teams

Preferred Qualifications

• MSc or PhD with a focus on digital design, computer architecture, or VLSI
• Experience designing digital control logic for RF beamformers, phased arrays, or similar high-performance systems
• Familiarity with high-speed serial interfaces, AXI/APB buses, and low-power design techniques
• Background in communications (e.g., 5G/6G, satellite) or radar system requirements
• Scripting (Python/Tcl) for design automation and flow development
• Prior work on phased-array or multi-antenna systems from concept through fielded product

Why Roguebeam

This is a rare ground-floor opportunity. Joining a startup at this stage means your work has a direct, visible effect on whether the company succeeds—and a corresponding upside as we grow. Because we build the entire system in-house, you'll see your RTL designs integrated into real phased arrays and deployed in working systems, not handed off and forgotten. You'll have real ownership and a seat at the table on technical direction.

This position requires access to information controlled under ITAR/EAR; applicants must be U.S. persons as defined in 22 CFR 120.62.