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Sr Engineer II - Physical Design

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Onsite

Sr Engineer II - Physical Design

Microchip Technology Inc.

Sr Engineer II - Physical Design

Skills

Python

1 month ago

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Important information


Contract type:

Permanent

Location:

Bengaluru, Karnataka, India

Work mode:

Onsite

Published on:

13 October 2026

What they need


Job highlights

  • The candidate should have experience with Physical Design tools
  • The candidate should have in depth knowledge of Innovus / ICC2 tool execution
  • Static Timing / Crosstalk Analysis and timing closure . Must have an understanding of Synthesis / DFT concepts and flow .
  • Experience in working with analog IP,hard and soft macros and delivering hierarchical design projects .

Job Description

Microchip AES Design team looking for an experienced and motivated Physical Design Engineer to implement RTL2GDSII for larger SOCs. As a member of Physical Design team, you will be responsible for place and route, timing closure and physical verification checks for multiple blocks and top level. The candidate should have experience with Physical Design tools. The candidate should have in depth knowledge of Innovus/ICC2 tool execution.

Location: Bangalore, India

Responsibilities

  • Floor-planning, Place Route and CTS using physical design tools like Innovus and ICC2.

  • Physical verification and IP Integration

  • Physical Design Flow and Methodology.

  • IR and EM checks.

  • Ability to lead Junior team members along with the project execution.

  • Use metric-driven techniques to help ensure first-pass working silicon.

  • Communicate regularly with the implementation and project team to resolve issues, and communicate status to leads

  • Occasional travel needed.

    Qualifications

This position requires at least BE/B.Tech/M.Tech in Electronics with 7+ years of Physical Design experience in a fast-paced environment with following experience.

  • Expertise in Physical Design activities: Floor-planning, CTS, PR, Extraction, Power IR/EM, Physical Verification (DRC/LVS) and Signal Integrity
  • Advanced knowledge of place and route methodologies and low power methodologies.
  • Static Timing/Crosstalk Analysis and timing closure
  • Must have an understanding of Synthesis/DFT concepts and flow
  • Experience in working with analog IP, hard and soft macros and delivering hierarchical design projects
  • Expertise with Backend Tools (Innovus or ICC2, Calibre or PVS, PrimeTime or Tempus, Redhawk or Voltus, Starrcxt or QRC)
  • Strong programming knowledge in Perl, TCL, and/or Shell and Python Scripting
  • Excellent oral and written communications skills in order to work with teams across the globe

Travel Time: 0% - 25%

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

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