Sr. Memory Design Engineer (Terafab)

What to Expect

We are building Terafab, a vertically integrated semiconductor factory at an unprecedented scale. The facility houses logic, memory, packaging, test, and lithography mask production under one roof, optimized for rapid iteration and maximum compute density per square foot.

We are looking for a Senior Memory Design Engineers/Lead to own LPDDR and HBM memory design at Terafab, our advanced silicon fabrication and design center. This is a rare opportunity to build a memory design discipline from the ground up, shape the memory architecture behind next-generation Tesla and SpaceX silicon, and hire the team that will execute on it.

You will operate at the intersection of process technology, IP vendor ecosystems, and system-level silicon design — translating ambitious product requirements into a memory roadmap that is fast, manufacturable, and scalable across Tesla and SpaceX programs.

What You’ll Do

• Lead LPDDR and HBM memory design at Terafab, from architecture through implementation and qualification

• Partner with Tesla and SpaceX silicon design teams to define memory requirements and specifications for current and future silicon products

• Engage directly with external memory and IP vendors to enable and optimize their designs for the Terafab process technology

• Hire, build, and lead a world-class memory design and development team, setting technical direction and engineering standards from day one

• Drive trade-off decisions across performance, power, area, and cost to meet aggressive product timelines

• Establish design methodologies, flows, and best practices for memory design at Terafab as the discipline scales What You’ll Bring

• Degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience

• Extensive experience in memory module design including LPDDR and/or 3D DRAM, and/or HBM. Deep understanding of memory cell architecture and protocols (LPDDR4x/5x/6). Experience in custom memory bit-cell design and layout will be a plus

• Expertise in Digital & Analog design including ultra-high speed signal integrity architecture. Deep knowledge of equalization & calibration, Eye-Mask testing, On-Die Termination (ODT) tuning. Skills in designing power delivery networks for low power design (DVFSL), Link ECC, on-die ECC, and designing around Per-Row Activation Counting (PRAC) protocol

• Track record of taking silicon memory designs from architecture through tape-out and silicon bring-up

• Hands-on experience working with memory or IP vendors to integrate and qualify third-party IP on a target process node

• Deep understanding of process technology considerations affecting memory design (timing, power, signal integrity, yield)

• Prior experience leading engineers or building a technical team, with the ability to hire top talent

• Strong cross-functional collaboration skills, with experience working alongside SoC/ASIC architecture and design teams