Sr. MSP Input - Supplier Inputs Professional

• Minimum Qualification Required: B.E./B.Tech in Electronics, M.Tech
• Candidate Skill: Digital Analog Circuits Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Strong understanding of digital, analog and CMOS circuit concepts.
• Candidate Skill: SystemVerilog UVM Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Develop and maintain UVM-based verification environments and testbenches.
• Candidate Skill: Verilog Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: RTL modeling, functional verification and simulation.
• Candidate Skill: CMOS Concepts Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Apply CMOS design concepts in digital and mixed-signal verification.
• Candidate Skill: Pre-Silicon Verification Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Perform block, subsystem and full-chip pre-silicon verification.
• Candidate Skill: Gate Level Simulation (GLS) Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Execute GLS for timing and functional validation.
• Candidate Skill: SystemVerilog Assertions (SVA) Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Develop assertions and verify protocol and functional behavior.
• Candidate Skill: Debug Root Cause Analysis Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Analyze waveform failures and resolve verification issues.
• Candidate Skill: Regression Execution Optimization Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Manage regression runs and optimize verification flow.
• Candidate Skill: EDA Tools Collaboration Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Work with industry-standard EDA tools and collaborate with cross-functional teams.
• Candidate Skill: Strong SV/UVM Expertise Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Hands-on ownership of advanced SystemVerilog/UVM verification.
• Candidate Skill: SoC / Full-Chip Pre-Silicon Ownership Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: End-to-end ownership of SoC and full-chip verification.
• Candidate Skill: DRAM Verification Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Verify DRAM and memory subsystem functionality.
• Candidate Skill: Proven Debug Depth Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Resolve complex functional and integration issues.
• Candidate Skill: Regression Management Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Plan, execute and analyze regression results.
• Candidate Skill: EDA Tool Flow Execution Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Execute simulation, automation and verification tool flows

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