Sr Physical Design Engineer

Job highlights

• Shift Type: 1st Shift / Days
• Required Travel: Yes,10% of the time.

Responsibilities

• Own and drive full-chip and block-level PV signoff activities.
• Perform and debug:
  • Design Rule Check (DRC)
  • Layout Versus Schematic (LVS)
  • Parasitic Extraction (PEX)
  • PERC/ERC checks
  • Antenna verification
  • Density and DFM checks
• Analyze and resolve complex PV violations while maintaining schedule commitments.
• Review and implement foundry rule deck updates.
• Work with layout and design teams to achieve clean signoff.
• Develop methodologies and automation to improve PV productivity and turnaround time.
• Support tapeout readiness reviews and signoff documentation.
• Perform Electromigration (EM) and IR Drop analysis on digital, analog, and mixed-signal designs.
• Define power integrity verification strategies for blocks and full-chip designs.
• Analyze static and dynamic IR drop issues and recommend corrective actions.
• Debug EM violations and optimize power grid structures.
• Correlate simulation results with design requirements and reliability specifications.
• Collaborate with circuit, package, and PD teams for power delivery optimization.
• Track and close reliability signoff requirements before tapeout.
• Develop scripts and utilities using Python, Tcl, Shell, or SKILL to automate PV and EMIR flows.
• Develop dashboards and reporting mechanisms for signoff metrics.
• Drive continuous improvements in PV and EMIR methodology.
• Interface with:
  • Physical Design teams
  • Layout teams
  • Circuit designers
  • CAD/EDA teams
  • Foundry support teams
• Participate in design reviews, signoff reviews, and tapeout planning meetings.
• Mentor junior engineers and provide technical guidance.

Job Type and Travel

• Job Type: Experienced
• Required Travel: Yes, 10% of the time
• Shift Type: 1st Shift/Days

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