Sr Principal Application Engineer – Digital Verification

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

• Act as a tech consultant to lead and support Cadence digital verification solution for customer projects or pre-sales engagements
• Work closely with the sales team to identify, qualify, and scope opportunities for Cadence’s digital functional logic verification solutions.
• Understand customer goals and objectives, and plan, execute, and manage key technical evaluations in close collaboration with customers and internal teams.
• Proactively engage with existing and prospective customers to ensure successful adoption and deployment of Cadence verification technologies.
• Summarize project activities, status, and outcomes, and report effectively to management while sharing knowledge and best practices within the team.
• Train, ramp-up and accompany customer project to ensure successful execution and adoption.
• Deliver basic and advanced trainings, technical presentations, and product demonstrations as required.
• Provide deep technical expertise to address complex customer issues and inquiries that require expert‑level support.

Requirements:

• Bachelor’s degree or higher in Computer Science, Electrical Engineering, or a related field, with10 + years of relevant industry experience.
• 10+ years of hands‑on experience and strong expertise in hardware design and/or verification methodologies.
• Solid hands‑on verification experience using UVM, SystemVerilog, Verilog, VHDL, SystemC, and SystemVerilog Assertions (SVA).
• Hands‑on experience with Cadence Verification IP or Jasper is a strong plus.
• Good understanding of code coverage and functional coverage concepts, tools, and technologies.
• Strong communication skills in English, with the ability and motivation to work in a global, customer‑facing environment with customers and internal business unit teams.
• Valid passport with no travel restrictions; willingness to travel as required.

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