Sr Principal Design Engineer - 高速接口

该职位来源于猎聘 Key Responsibilities

• Responsible for scheduling, designing, developing, and supporting high speed protocol products such as PCIe, UEC, ethernet etc used on Cadence hardware-based emulation platforms.
• Perform as individual contributor for RTL design, UVM verification, FPGA/PROC/Board debug, documentation etc.
• Collaborate with other developers and domain experts in a fast-paced R&D environment.
• Participate in complex system debugging, testing, and performance optimization.
• Mentor junior engineers on logic design, verification, and FPGA/board debug.

Job Requirements

• The position requires MSEE, or equivalent, with a minimum of 10 years significant experience in designing complex protocols and/or hardware systems.
• Fluent and extensive RTL design knowledge using Verilog/SystemVerilog is required along with experience using RTL verification tools and flows.
• Must excel in RTL design based on protocol Specification and datasheet, demonstrate solid debugging experience/skills.
• Deep understanding of one high speed protocol knowledge is a PLUS.
• Verification experience using UVM to buildup complex projects involving Cadence VIP is a PLUS.
• Programming experience with scripting languages like C/C++, Perl, TCL, Python etc is a PLUS.