Sr Principal Engineer- Digital Design

Job Summary:

We are seeking an experienced Senior Principal Engineer - Digital Design to lead the micro-architecture, design, and execution of next-generation UA Link Switch solutions within the Memory Interface Division (MID). The ideal candidate will bring deep expertise in high-speed digital system design and SoC development, with a proven track record delivering complex silicon products from architecture through production.

This role requires strong technical leadership in defining and implementing scalable switching and interconnect architectures that enable high-bandwidth, low-latency connectivity for AI, HPC, and memory-centric systems.

Key Responsibilities:

• Lead digital architecture and design activities for UA Link Switch products.

• Define and drive microarchitecture, RTL design, integration, and performance optimization of high-speed switching fabrics and interconnect subsystems.

• Collaborate with architecture, verification, firmware, physical design, signal integrity, and system teams to ensure successful product execution.

• Drive end-to-end development from requirements definition through silicon bring-up and product qualification.

• Provide technical leadership across multiple engineering teams and mentor senior engineers.

• Analyze performance, power, area, and scalability trade-offs to meet aggressive product goals.

• Participate in architectural reviews, design audits, and technical roadmap planning.

• Work closely with ecosystem and standards teams to align product implementation with evolving industry standards. Qualifications

• Bachelor s, Master s, or Ph. D. in Electrical Engineering, Computer Engineering, or related discipline.

• 15+ years of experience in digital ASIC/SoC development.

• Strong experience in one or more of the following areas:

1. High-speed digital design
2. SoC architecture and integration
3. Switching fabric design
4. Network-on-Chip (NoC)
5. High-speed interconnects
6. Memory subsystem design
7. Microcontroller-based systems
8. High-bandwidth data movement architectures

• Deep understanding of RTL design using Verilog/SystemVerilog.
• Experience with modern ASIC development flows including synthesis, STA, low-power methodologies, and silicon bring-up.
• Strong debugging and performance analysis skills.
• Demonstrated ability to lead complex technical programs and influence cross-functional teams.

Preferred Qualifications:

• Prior experience in: High-speed SerDes-based systems, Switching fabrics and packet processing architectures, Memory interface technologies, AI/HPC interconnect solutions, PCIe, CXL, Ethernet, UCIe, or related high-speed protocols.
• Experience developing large-scale SoCs for networking, compute, storage, or memory applications.
• Understanding of system-level architecture and board-level considerations for high-speed designs.
• Experience leading geographically distributed engineering teams.
• Strong communication and stakeholder management skills.

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