Sr . STA / Timing constraints Engineer

Job Summary

Advance your career. Advance the world.

Whether you're designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we'll advance your career.

Key Responsibilities

• Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff

• Ensuring constraints quality (SDC) using industry tools like Fishtail, GCA

• Well versed with timing signoff methodology and corner definitions

• Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks

• Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts)

• Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip.

• Ensuring full chip level Interface timing closure along DRV closure

• Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure

Preferred Experience

• 5+ years of experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows.

• Experience with analyzing the timing reports and identifying both the design and constraints related issues.

• Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc.

• Experience in timing closure of high frequency blocks subsystems (> GHz range )

• Strong Understanding of DFT modes requirements for timing signoff

• Good understanding of physical design flow and ECO implementation.

• Strong understanding of SDC constraints, OCV,AOCV,POCV analysis.

• Strong TCL/scripting knowledge is mandatory.

Academic Credentials

• Bachelors or Masters degree in computer engineering/Electrical Engineering

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