Sr Staff VLSI Design Engineer

Job responsibilities:

• Hands-on contributions coding C++ System C models test creation
• Debug issues in Firmware environment
• Validating the developed model using systemC/SV/UVM testbench
• Debug failures and root-cause it by interacting with other teams/groups Etc.
• The candidate will also have to mentor junior engineers Qualifications

Experience:

13+ Years of the relevant work experience

• Functional Modeling Verification:

• Hands-on experience in C++ System C based Model development/test creation

• Prior Experience with C based Tests/Test bench development

• Python coding would be a plus

• Knowledge on NAND concepts will be an advantage

• Knowledge on Memory and Digital Design Concepts would be preferable

• (SRAM/DRAM/ROM/Flash) Circuits/Logic knowledge us a plus

- Languages Expertise

• C, C++, Python,System C,
• Verilog/SystemVerilog/UVM will be a plus

- Tool Expertise

• VisualStudio, Git, Bitbucket

Education Soft skills:

• Bachelors/Masters from a reputed College/University with Electronics and communication/Embedded Systems background
• Strong Problem Solving
• Efficient Communication
• Team Leading Mentoring skills

Disclaimer: This job posting and Location has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.