SRAM EDA Engineer

Job Title:

SRAM EDA Engineer

Team: Enablement / SRAM

Location: Albany (NY), Santa Clara (CA), Tokyo (Japan), or Chitose (Japan) -

Overview

About the Role

Rapidus is building the world’s most advanced semiconductor manufacturing ecosystem, with leading edge 2nm and beyond process technologies. We are seeking an SRAM Design Automation Engineer to architect, develop, and scale automation flows for high-performance, high-density SRAM macros and memory compilers used across cutting edge SoCs.

This role requires basic understanding of transistor level SRAM circuits, advanced node variability, and deep understanding of custom IC EDA automation. You will develop design flow that can robustly generate, assemble, simulate, verify, characterize, and deliver SRAM macros across multiple architectures using assist schemes, and PPA targets—optimized for 2nm/1.4nm-class design rules, device models, and reliability constraints.

You will work at the intersection of circuit design, CAD/EDA, physical design, DTCO, and process technology, enabling Rapidus customers to achieve first time right silicon on the most advanced nodes.

Responsibilities

SRAM Compiler & Flow Development

• Develop and maintain SRAM memory compiler flows supporting configurable architectures, banking structures, aspect ratios, redundancy, and assist circuits.
• Develop and maintain SRAM memory compiler flows supporting configurable architectures, banking structures, aspect ratios, redundancy, and assist circuits.
• Implement automation for schematic, layout, and abstract view generation (LEF) using Cadence SKILL and custom infrastructure.
• Build scalable frameworks to support multiple device options (FinFET, nanosheet, multi-Vt, multi-height cells) and advanced assist techniques required at 2nm and beyond.

Advanced Node Simulation & Characterization

• Develop automated Spectre/HSPICE/SPICE simulation environments for read/write stability, SNM, write margin, disturb analysis, Vmin characterization, and variation-aware metrics.
• Integrate Monte Carlo, LVF/AOCV/POCV, and nanosheet-specific variability models into automated flows.

Create robust post-processing scripts to generate timing, power, leakage, stability, reliability, and yield reports across PVT corners and statistical distributions.

• Physical Verification & Extraction
• Build automated flows for DRC, LVS, ERC, PEX, and post-layout validation optimized for 2nm-class design rules (nanosheet spacing, EUV constraints, restrictive patterning).
• Debug SRAM netlists, hierarchy, device connectivity, extraction issues, and simulation setup across multiple views.

Automation Infrastructure

• Develop reusable automation frameworks using SKILL, Python, Tcl, Perl, Shell, and/or C/C++.
• Integrate SRAM flows into memory compilers, custom-IC automation environments, and Rapidus design enablement toolchains.
• Ensure flows scale across large configuration spaces, high-capacity compilers, and multi-project customer environments.

Cross-Functional Collaboration

• Work closely with SRAM circuit designers, layout teams, CAD/EDA engineers, DTCO teams, process/device engineers, and customer enablement groups.
• Partner with Rapidus process technology teams to incorporate 2nm/1.4nm device models, reliability constraints, BEOL RC characteristics, and assist requirements into automation flows.

Required Qualifications

• BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field.
• Professional or academic experience with SRAM or memory circuit design, memory compilers, or custom-IC automation.
• Experience with Cadence Virtuoso, custom IC design flows, and layout automation.
• Proficiency with Cadence SKILL or equivalent EDA automation languages.
• Experience with Spectre, HSPICE, or SPICE simulation environments.
• Strong Linux/Unix background with scripting experience.
• Experience with data analysis automation for large simulation datasets.

Preferred Qualifications (Highly Desirable for Rapidus 2nm/1.4nm Nodes)

• Experience with advanced-node variation modeling (LVF, AOCV, POCV, Monte Carlo).
• Experience with SRAM assist circuits (WL underdrive, BL lowering, VDD collapse, negative bitline, boosted write).
• Knowledge of DTCO, design rules, restrictive patterning, and EUV-specific constraints.
• Experience developing and supporting memory compilers or large-scale custom automation frameworks.
• Understanding of yield modeling, redundancy schemes, and reliability verification for advanced nodes.

About Rapidus

Rapidus Corporation, founded in 2022, is Japan-led initiative to build a world-class advanced logic semiconductor foundry. With a bold vision to accelerate innovation, we are pioneering cutting-edge logic semiconductor research, development, design, and manufacturing to transform the global semiconductor industry.

Why Join Us

You will play a central leadership role in building the world’s most advanced 2nm and next ‑ generation enablement ecosystem , shaping the foundation for future semiconductor innovation.

You will focus on the implementation stages (Synthesis and PnR) of the digital reference flow. Additionally, you will lead the adoption of next-generation automation tools, including AI/ML-driven DSE (Design space exploration)

Good Faith Salary Range

$130,000 - $285,000 annually

*The salary range provided is a good-faith estimate for this position in New York at the time of posting. Actual compensation will be determined based on factors including, but not limited to, relevant experience, skills, qualifications, education, certifications, and work location.

Benefits

• Comprehensive Health, Dental and Vision coverage, fully at company's expense (no deductibles)
• 401k with no employer match