SRAM Layout Design Engineer

Position : Senior SRAM Layout Design Engineer

Location -Santa Clara, CA (Onsite Role)

Contract Position

• This is onsite 5 days in week for initial 3-4 months till manager gets comfortable with worker performance and later it may change to 3-4 days in week onsite
• 2 positions to be filled
• 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.
• Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.
• Not open to candidates who has experience with more that 5nm dimensions as they will not be able to pick the work this team is doing
• Open to nonlocal candidates who can relocate at own expense to be onsite from day 1
• 2 interviews, first virtual second round in-person panel interview with 3-4 team members
• 12-month contract, possibility to extend depending on performance and Business needs
• Will work on custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
• Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment is required
• Solid understanding of SRAM and memory layout principles.
• Experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools is required
• Knowledge of layout automation or AI tools is a definite plus.
• Bachelors preferred
• Please check if they applied, interviewed for Nvidia roles before, such candidates will not be accepted
• Candidates who are not working for past 1-2 years will not be accepted

Pay: $100.00 - $112.00 per hour

Work Location: In person