Sr.Lead Sta Engineer

Job Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Overview

As a Sr.Lead (STA) Engineer, you will be a key contributor to SoC level timing closure, working closely with RTL, CAD, DFT and physical design teams. You will drive timing analysis and closure for complex, multiGHz designs across block, cluster, and fullchip hierarchies, ensuring aggressive frequency and power targets are met.

Responsibilities

• Work closely with RTL team to understand different protocols (DDR, PCIE, UCIE etc..), critical paths, and performance goals, and to define, implement, and validate timing constraints.
• Perform STA for highperformance designs at block, cluster, and SoC/toplevel hierarchies across multiple modes, corners, and scenarios.
• Analyze timing on frequencycritical paths and collaborate with RTL and DFT teams to drive logic and microarchitectural fixes.
• Provide actionable timing feedback to blocklevel and toplevel physical design engineers
• Generate and review timing ECOs (logic and physical) to close setup, hold, noise, and crosstalk violations.
• Need to lead STA team for a given project.

Preferred Qualifications

• Bachelors or masters degree in electrical/Electronic Engineering with 5-9 years of handson experience in STA and timing closure.
• Strong experience with STA and timing closure for highperformance SoCs.
• Expertise in multiclock, multidomain designs with aggressive frequency targets.
• Experience in deep submicron technology nodes and advanced process technologies.
• Proven experience performing STA on large CPU/SoC designs with multi-scenario and signoffquality closure.
• Familiarity with standard cell libraries, transistor fundamentals, and worstcase corner selection for timing signoff.
• Strong understanding of industrystandard synthesis, and tapeout flows.
• Excellent communication skills to work effectively with RTL designers, PD, and CAD teams.
• Indepth knowledge of timing effects such as noise, crosstalk, OCV/variation, and their impact on designs.
• Familiarity with both Tempus and Primetime STA tools.
• Familiarity with scripting languages like perl, tcl, awk etc..