Sta Engineer

STA Engineers

Experience: 820 years

Location: BLR/HYD

Mode : WFO

NOTE: Only Immediate candidates will be entertained

• Deep expertise in timing architecture and signoff
• Define timing architecture and establish timing signoff methodology for complex chip designs
• Provide expert consultation on advanced timing challenges including multi-die timing, 3D-IC timing, and advanced node effects
• Drive innovation in timing analysis methodologies leveraging machine learning and advanced statistical techniques
• Lead timing correlation studies between different tools and silicon to improve prediction accuracy
• Collaborate with architecture and design teams to influence chip architecture for timing optimization
• Contribute to industry standards and best practices through technical publications and conference presentations
• Develop intellectual property through patent submissions in timing analysis domain
• Provide technical leadership and mentorship across the timing engineering organization
• Conduct technology evaluation and pathfinding for next-generation timing analysis capabilities