STA Engineer

Role: STA Engineer (Static Timing Analysis)

Location: San Jose, CA (Onsite)

Job Type: Full-Time + Benefits

Experience: 8+ Years

Job Summary

We are seeking an experienced STA Engineer to develop and validate timing constraints, perform static timing analysis, and drive timing signoff for complex SoC designs at advanced technology nodes. The ideal candidate will have strong expertise in industry-standard STA tools, timing constraints, clock tree optimization, timing ECOs, and ASIC design flows.

Key Responsibilities

• Develop, validate, and maintain timing constraints for complex SoC and hierarchical designs.
• Perform static timing analysis using industry-standard tools such as Synopsys PrimeTime and Cadence Tempus.
• Define and implement timing signoff methodologies, including process corners, derates, and timing uncertainties.
• Conduct pre-route timing analysis and quality-of-results (QoR) assessments.
• Automate timing analysis and signoff processes using Tcl and Perl scripting.
• Collaborate with physical design teams on clock tree synthesis, planning, and optimization for power-efficient designs.
• Perform timing ECO creation, analysis, and implementation to achieve timing closure.
• Ensure compliance with timing signoff checklists, methodologies, and project requirements.
• Support final timing signoff and resolve timing-related issues across the ASIC design flow.
• Work closely with RTL, synthesis, and place-and-route teams to address timing challenges.

Required Qualifications

• Bachelor's degree with 8+ years of relevant experience, Master's degree with 6+ years, or PhD with 3+ years of relevant experience.
• Strong experience in static timing analysis for complex SoC designs.
• Hands-on expertise with STA tools such as Synopsys PrimeTime or Cadence Tempus.
• Experience developing timing constraints for hierarchical designs.
• Strong knowledge of process corners, derates, uncertainties, and timing signoff methodologies.
• Experience with timing ECOs, timing closure, and final timing signoff.
• Proficiency in Tcl or Perl scripting for automation.
• Experience with synthesis tools such as Cadence Genus.
• Strong understanding of ASIC design flows, including RTL, synthesis, and place-and-route.
• Knowledge of clock tree planning, implementation, and optimization.
• Experience working with high-complexity silicon at advanced technology nodes.
• Excellent analytical, problem-solving, communication, and teamwork skills.

📩 Interested candidates can share their updated resume to [email protected]