STA Engineer Timing Constraints & Closure

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our top leading Manufacturing client. If you're interested and your experience matches the requirement, we'd love to hear from you.

Job Title: Engineering - Hardware Design Engineer 2

Location: Bangalore

Duration: 12 Months

Preferred experience:

• 4-5 years of experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows.
• Experience with analyzing the timing reports and identifying both the design and constraints related issues.
• Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc.
• Experience in timing closure of high frequency blocks & subsystems (> Ghz range )
• Good Understanding of DFT modes requirements for timing signoff
• Good understanding of SDC constraints, OCV, AOCV, POCV analysis.
• Strong TCL/scripting knowledge is mandatory.