STA Timing Constraints Engineer 0421

Job highlights

• 3-6 years experience with expertise in Static Timing Analysis, timing constraints (SDC), SoC/block-level constraint integration, and scripting in Tcl/Perl/Python
• Develop and verify block and SoC-level timing constraints, integrate IP timing constraints, and debug timing issues

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.

Position: SoC Timing Constraints Engineer
Experience: 3-6 Years

Location: Bangalore

Contract Tenure : 12 months

Job Description:
We are looking for an engineer with a strong understanding of Static Timing Analysis (STA), timing constraints, and VLSI design flow. Responsibilities include developing and verifying block-level and SoC-level timing constraints, integrating IP timing constraints into SoC constraints, and debugging timing constraint issues.

Required Skills:

• STA concepts and timing constraints (SDC).
• SoC and block-level constraint development and integration.
• VLSI design flow knowledge.
• Familiarity with Verilog, Liberty (.lib), LEF, and GDS.
• Basic knowledge of DRC/LVS physical verification.
• Scripting skills in Tcl, Perl, Unix Shell, or Python.