Staff Digital IC Design Engineer

Responsibilities

• Design and develop digital IP and SoC interconnect architectures, including Network-on Chip (NoC) components and communication interfaces.
• Define and implement microarchitecture and RTL using Verilog/SystemVerilog.
• Develop and optimize interconnect functionality involving topology, routing, arbitration, flow control and Quality of Service (QoS).
• Support integration of interconnect and IP subsystems with processors, accelerators, cache and memory controllers.
• Collaborate with architecture, design verification and physical design teams to ensure functional correctness and successful implementation.
• Perform performance analysis and optimization relating to bandwidth, latency, power, performance and area (PPA).
• Support synthesis, timing analysis, design reviews, debugging and silicon delivery activities.
• Contribute to technical discussions, design methodologies and engineering best practices as the local team expands.

Qualifications

• Master's degree in Microelectronics, Electrical/Electronic Engineering, Integrated Circuits, Computer Engineering or a related discipline.

Required Skills

• Strong hands-on experience in digital IC, ASIC, SoC or IP design, preferably with 8 to 10 years of relevant engineering experience.
• Proficiency in Verilog/SystemVerilog with practical RTL design and implementation experience.
• Experience in IP architecture, microarchitecture definition or complex digital logic development.
• Familiarity with SoC interconnect, bus architectures or communication protocols such as AXI, AMBA, PCIe, ACE or CHI.
• Understanding of digital design flows, including synthesis, timing analysis, low-power design and verification.
• Ability to work independently, solve complex technical challenges and collaborate effectively with cross-functional engineering teams

Preferred Skills

• NoC architecture, interconnect fabric or crossbar design.
• Routing, arbitration, flow control, QoS or congestion management.
• Cache coherency, memory subsystems or CPU/GPU/NPU integration.
• Performance modelling, bandwidth and latency optimization.
• ASIC tape-out or production silicon experience.
• Technical mentorship or IP/subsystem ownership