Staff Engineer, PCIe PHY/Link Analysis

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Our technology solutions power the tools you use every day-including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.

Please Note:

To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.

Advancing the World's Technology Together

Our technology solutions power the tools you use every day-including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.

Our technology solutions power the tools you use every day-including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.

Our technology solutions power the tools you use every day-including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.

Our technology solutions power the tools you use every day-including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.

At the Technology Enabling Development Lab (TED), our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung's breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures.

We are looking for a dynamic, self-motivated engineer to develop and support our cutting-edge Enterprise and Data Center SSD products. The ideal candidate will possess comprehensive expertise across the full PCIe protocol stack - from the Physical Layer (PHY) through the Data Link Layer and up to the Transaction/Transport Layer - with a proven track record in hardware/firmware design, protocol implementation, and complex link bring-up and debugging. This position is based in San Jose, California.

What You'll Do

• Protocol Stack Analysis: Understand PHY/Link architecture, implementation, and integration of the PCIe protocol stack from the Physical Layer through the Data Link Layer to the Transaction/Transport Layer, in collaboration with internal H/W teams and external vendors.
• Link Bring-up & Training: Own LTSSM behavior, link training and equalization sequencing, PCIe enumeration, and configuration-space flows during device bring-up.
• Transaction/Transport Layer: Analyze and validate TLP/DLLP handling, flow control, credit management, ordering rules, ACK/NAK and replay, error handling (AER), and end-to-end data integrity across the stack.
• Debug & Optimization: Analyze and debug complex PHY, Link, and Transport layer issues during bring-up and sustaining stages of NVMe SSD products, from Gen1 to the latest generation (Gen7), covering protocol (LTSSM / PCIe enumeration) and PCIe feature-related issues.
• Compliance & Standards: Participate in and support industry PHY/Link compliance tests, including PCI-SIG events.
• Field Support: Provide onsite support for PHY/Link related tasks at customer sites and labs.
• Travel: This position requires up to 25% business travel.

What You Bring

• BS in Computer/Electrical/Electronic Engineering or Computer Science, and 8+ years of relevant experience in hardware or a MS in Computer/Electrical/Electronic Engineering or Computer Science with 5+ years of relevant experience is required.
• Protocol Expertise: Deep proficiency with the PCIe protocol spanning the entire architecture from the Physical Layer through the Data Link Layer to the Transaction/Transport Layer.
• Link Layer Mastery: Strong hands-on knowledge of LTSSM, link training/equalization, PCIe enumeration, flow control, replay/retry, and error handling (AER).
• PHY Awareness: Working knowledge of PHY-layer operation (CDR to Equalizer such as VGA, CTLE, DFE, FFE, DSP, etc ) sufficient to root-cause link issues that cross the PHY/Link boundary.
• Firmware & Debugging: Solid experience in C/C++ for embedded systems, and expertise with UART/JTAG/ICE debuggers and general firmware debugging techniques.
• Analysis Tools: Strong experience with PCIe protocol analyzers, logic analyzers, and signal analyzers for link and transaction-level debug.
• Collaboration: Ability to work effectively within a multi-functional team environment.

Preferred Skills

• Knowledge on SI/PI for PCIe
• Extended Protocols: Proficiency in NVMe, CXL, or SAS/SATA protocols is a significant plus.
• Validation: Experience in both pre-silicon and post-silicon SoC validation.
• Power Management: Experience with PCIe power management (ASPM, L1 substates) and low-power link states.

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When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.

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