Staff Engineer Verification

Job highlights

• Should be able to develop IP / SoC test benches,Experience and knowledge in Verification of IPs / SoCs related to different applications,Good Knowledge in Power aware verification and Gate level verification is preferable
• Good understanding of ASIC verification concepts and techniques
• Very good knowledge of Verilog / System Verilog and UVM

Verification Requirements creation at IP/SoC level as per the design requirements and UVM Test benches creation
Job Description
In your new role you will:
Leading sub tasks in IP/SoC Verification
Contributes significantly for the Verification of complex IPs/SoCs
Verification Requirements creation at IP/SoC level as per the design requirements and UVM Test benches creation
Support in building verification infrastructure at the IP/Chip level as per the requirements
Support in different areas of SoC Verification: RTL, Power Aware and Gate Level Verification
Your Profile
You are best equipped for this task if you have:
Bachelor's 6 to 7 yearsexperience, Masters 5 to 6 years 'experience
Good understanding of ASIC verification concepts and techniques
Very good knowledge of Verilog/System Verilog and UVM
Should be able to develop IP/SoC test benches, Experience and knowledge in Verification of IPs/SoCs related to different applications, Good Knowledge in Power aware verification and Gate level verification is preferable
Knowledge on Ethernet (IEEE 802
3), MIPI protocols, Display Port is preferable, Contact:
swati
gupta@infineon,
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