Staff Layout Engineer

About the role

IC Layout Engineer responsible for understanding and applying all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout. You will schedule time-line & layout floor-planning, complete quality layout and verification within planned schedule, and get up to speed quickly for new methodologies while communicating well with others in the library team.

Key responsibilities

• Understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout
• Schedule time-line & layout floor-planning
• Complete quality layout and verification within planned schedule (without supervision for experienced engineer)
• Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team
• Lead or train a team of junior engineers
• Lead new technology reviews to compile documentation of layout methodology, layout flow and guidelines

About you

• Minimum 8 years of IC layout experience
• Strong layout knowledge with experience in submicron processes (16nm, 7nm, 5nm, 2nm, A14 and below)
• Experienced in digital (standard cell, memory, I/O) layout
• Strong experience in memory layout design and physical verifications, including LVS, DRC, ERC, Antenna, and Electro Migration in CMOS processes
• Experienced in Cadence Layout tools VIRTUOSO (XL, VXL or EXL), and CALIBRE verification tools
• Good experience in Floor-planning, hierarchy layout and chip integration
• Self-reliant, with the ability to work independently as well as in a team
• Good leadership quality in project management
• Experienced in analog layout is a plus
• Experience in memory compiler is a plus

About us

Library Group is a part of Central Engineering Group. In Library Group, we focus on circuit design for memory, I/O (Input/Output), and Standard Cells.