Staff RTL Design Engineer

Key Responsibilities

• Own the PCIe subsystem/IP micro-architecture and RTL design from specification through integration and sign-off, ensuring high-quality and timely delivery.
• Develop high-performance Verilog/SystemVerilog RTL for complex SoC/IP/subsystems, focusing on efficiency and reliability.
• Design and implement multi-clock, high-bandwidth, latency-sensitive architectures, optimizing for performance and resource utilization.
• Drive RTL quality through comprehensive verification processes, including lint, CDC/RDC, and formal verification, maintaining design integrity and performance standards.
• Collaborate with architecture, verification, physical design, and firmware teams to ensure seamless integration and functionality of designs.
• Contribute to the design of clock/reset, power-management, and HW/SW interfaces, enhancing system performance and reliability.
• Mentor and guide junior engineers, fostering a culture of excellence and continuous improvement within the team.
• Participate in design reviews and provide expert feedback to ensure the highest standards of design quality and innovation.

Overview

• The role of Staff Engineer, RTL Design, involves developing high-performance System on Chips (SoCs) and chiplets with a focus on AI, High-Performance Computing (HPC), and Networking applications.
• This position is crucial in driving the design and integration of PCIe subsystems and IP micro-architecture.
• Situated in the semiconductor sector, this role is vital to advancing cutting-edge technology and delivering top-tier solutions.
• The successful candidate will work in a dynamic environment, collaborating closely with architecture, verification, physical design, and firmware teams.
• The position requires not only extensive technical expertise but also leadership in design innovation and quality assurance.
• Candidates will be responsible for owning the RTL design process from specification through to integration and sign-off, ensuring the delivery of high-quality design solutions.
• The position is based in Bangalore and is suited to a Level 5 professional with 9-12 years of experience in the field.
• With a strong emphasis on PCIe RTL design, this role demands a proactive approach to problem-solving and innovation in multi-clock, high-bandwidth, and latency-sensitive architectures.
• The role necessitates a hands-on approach to developing high-performance Verilog/SystemVerilog RTL, with a focus on enhancing design efficiency and performance.
• The candidate will contribute significantly to clock/reset, power management, and HW/SW interface designs, aiming to optimize system performance and reliability.
• This is an exciting opportunity to contribute to the development of next-generation semiconductor technologies.
• The Staff Engineer will play a key role in driving RTL quality through various verification processes, including lint, CDC/RDC, and formal verification, ensuring design integrity and performance.
• As a technical leader, the candidate will also have the opportunity to guide and mentor junior engineers, fostering a culture of excellence and innovation.
• This role offers a unique opportunity to work at the forefront of semiconductor technology, contributing to projects that shape the future of AI and networking solutions.
• The successful candidate will bring a wealth of experience and a proven track record in RTL design, particularly with PCIe subsystems, to ensure the continued success and innovation of our technology solutions.

Requirements

• 8+ years of relevant RTL design experience, with a strong focus on PCIe RTL design.
• Proficiency in Verilog/SystemVerilog and micro-architecture design, with proven skills in developing complex SoC/IP/subsystems.
• Experience in AI, HPC, Networking, or high-performance SoCs, demonstrating the ability to deliver cutting-edge solutions.
• Hands-on experience with CDC/RDC, lint, and formal verification processes to ensure design quality and performance.
• Familiarity with other high-speed interfaces such as CXL, Ethernet, or UCIe is a plus, broadening the scope of design capabilities.
• Experience with secure boot, power management, clock/reset architecture, or embedded management processors adds significant value.
• Demonstrated leadership in leading PCIe subsystem RTL development, with the ability to guide and mentor junior team members.