Staff/Senior Staff Design Verification Engineer

• As a Design Verification Engineer at Lightmatter, you will find yourself at the heart of a dynamic, interdisciplinary team
• Your role will involve close collaboration with our digital design experts, using UVM testbench techniques to rigorously verify their designs
• Your responsibilities will include working alongside photonic and analog designers, gaining a deep understanding of their innovative designs, and applying Real Number Modeling (RNM) and AMS verification methods
• This critical function ensures the integrity of their work
• Your interaction with the Architecture team will be crucial in comprehending system requirements and spearheading performance verification
• This role offers a unique platform to enhance your skills across a spectrum of areas including UVM, AMS modeling, mixed-signal verification, post-silicon validation formal verification, emulation, and both performance modeling and verification
• Define and enhance the DV methodologies required for integrated digital, analog, and photonic devices with a strong emphasis on emulation for design verification
• Create and execute test plans to ensure high-quality tapeouts that meet functional and performance goals, while leveraging emulation where appropriate
• Collaborate with architects, DV engineers, digital designers, and analog/photonics designers to define validation flows
• Create reusable and scalable test bench components that enable efficient and effective verification
• Close coverage and finish all DV signoff requirements, with a focus on leveraging mixed signal simulations to achieve high coverage metrics
• Work on block level and full chip design verification
• Integrate analog design IPs from vendors and internal teams and develop verification environments for simulation and emulation
• Work with analog design engineers to create behavioral models for analog designs and with digital design engineers to integrate models/testcase/checkers into upper levels

Benefits

• Commuter benefit
• 401(K)
• Happy hour -Spend time together and build friendships
• Generous vacation policy and holidays
• Opportunity to learn from your peers and teach them what you know across electronics, photonics, machine learning, and more- Experience with simulators such as Xcelium, ModelSim, Questa, or VCS
• Expertise in developing with the UVM library
• Strong problem solver and collaborator
• 2+ years of experience in Python
• Minimum of 8 years of design verification and SystemVerilog experience
• Bachelor’s degree in Electrical Engineering, Computer Engineering, a related field, or equivalent experience
• Master’s degree or higher in Electrical Engineering, Computer Engineering, a related field, or equivalent experience with 6 years of relevant experience
• Experience with post-silicon validation and debug
• Experience with AMS verification