Lakshya Software Technologies Pvt. Ltd.
Static Timing Analysis: Lead (Chip Level)
Skills
3 days ago
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Important information
Contract type:
Permanent
Location:
Bengaluru, Karnataka, India
Work mode:
Onsite
Published on:
22 October 2026
What they need
Static Timing Analysis: Lead (Chip Level)
Experience: 10-15 yrs | Positions: 2
Responsibilities
∙Own chip-level STA, including constraint writing, quality checks, and budgeting analysis
∙Drive top-level timing closure and sign-off
∙Lead the STA team and coordinate with PD and design teams
Skills
∙Expert in PrimeTime/Tempus, SDC, and exceptions (CDC, false/multicycle paths)
∙OCV/AOCV/POCV, SI, and MCMM analysis at advanced nodes
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