Sivaltech
Synthesis & STA Engineer
Skills
3 years ago
Share this opportunity
Share this opportunity to other talents of your network:
✓ Offer them a visibility boost with clients.
✓ Help your contacts find their next job.
Important information
Contract type:
Permanent
Location:
Hyderabad, Telangana, India
Work mode:
Onsite
Published on:
13 October 2026
What they need
Job highlights
Required : Bachelors in Computer Engineering,Computer Science,Electrical Engineering,and / or related field .
Preferred : Masters in Computer Engineering,Computer Science,Electrical Engineering,and / or related field
Minimum 3 years of experience .
Experience with Synopsys tools for ASIC Synthesis and Timing Constraints and DFT implementation that includes MBIST and Scan .
Synthesis & STA engineers will perform RTL Synthesis to achieve the best Performance/Power/Area of the designs, DFT insertions that include MBIST and SCAN, setup Timing Constraints for functional and Test Modes, and Validation
These candidates will create Power Intent for the designs and verify power intent on RTL, run static Low-Power checks on gate level netlists, Verify Logic Equivalency Checks between RTL to Gates and Gates to Gates, setup signoff Static Timing Analysis and ECO flows and achieve timing closure working with the Design/DFT/PD teams, run Power Analysis and estimate power at RTL level, run Sign off Power Analysis on the P&R data, support the DV team to enable gate level simulations with SDF and UPF aware simulations, and support functional eco rollout with automated ECO flows
Qualification Requirements :
- Minimum 3 years of experience
- Experience with Synopsys tools for ASIC Synthesis and Timing Constraints and DFT implementation that includes MBIST and Scan
- Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks
- Experience with Verilog and System Verilog
- RTL design experience with Perl/TCL/Makefile scripting
- Experience with Power Analysis using Power Artist and PTPX
- Experience with full-chip static timing analysis through tapeout, gate level simulations, and Functional ECO implementation with Automated flows
Education Requirements:
- Required : Bachelors in Computer Engineering, Computer Science, Electrical Engineering, and/or related field
- Preferred : Masters in Computer Engineering, Computer Science, Electrical Engineering, and/or related field
Other offers great for you!
These companies are also looking for great profiles
Anderson RH
Ingénieur(e) Études – Applications Paiements & Services - Banque en ligne
Permanent contract
Paris, France
Hybrid
Skills
15 hours ago
Quick apply
Cherrypick
Ingénieur intégration système Windows / Infrastructure & Sécurité
700
Freelance
Paris, France
Hybrid
Skills
14 hours ago
Quick apply
Nexiqon
Chef de projet MOE Data Senior – Banque / Finance & Risques (H/F)
Permanent contract
Paris, France
Hybrid
Skills
13 hours ago
Quick apply
No company information available.