Einfochips
Synthesis Engineer
2 months ago
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Important information
Contract type:
Permanent
Location:
Bengaluru, Karnataka, India
Work mode:
Onsite
Published on:
24 August 2026
What they need
5 to 10 years of experience in RTL Synthesis, Timing Constraints / SDC checking / reviewing / small fixes / finding errors etc. Should have done at least 3 ASIC projects.
CDC, Lint clean up and automation with scripts.
Timing Report analysis, Static Timing Analysis
Tools :
Genus / FC : Synthesis, Optimization or DC compiler, DCTopo
Spyglass : Constraints checking / CDC Checking
LEC / Formality : Formal Verification, VCLP.
Primetime : Zero delay Timing analysis
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