System & FPGA Platform Engineer

EPIC ASIC is a Toronto-based semiconductor design company delivering end-to-end ASIC and SoC development, from architecture and RTL through tapeout and production. Our team brings extensive experience in developing advanced silicon solutions and supporting clients throughout the product development lifecycle.

We work on challenging designs spanning high-performance computing, custom ASICs, high-bandwidth data movement, power optimization, and hardware for AI and datacenter infrastructure. Our engineers collaborate across disciplines to solve demanding technical problems while balancing performance, power, area, reliability, and time-to-market.

At EPIC ASIC, we value technical excellence, collaboration, and practical engineering. We are building a team of engineers who enjoy working at the forefront of semiconductor technology and taking designs from concept through working silicon.

EPIC ASIC and our clients are seeking a System & FPGA Platform Engineer to own the path from architecture to a working system: FPGA proof-of-concept today, board/host/rack-level definition for silicon next.

What you will do

• Build and maintain the multi-FPGA prototype (AMD Versal / Alveo class, HBM and PAM4 transceivers) —Toronto will host one of two lab rigs
• Port and partition RTL to FPGA; timing closure, transceiver bring-up, host PCIe link, debug infrastructure
• Define system-level requirements: host interface, board, power, thermal, clocking/synchronisation across many accelerators
• Write bring-up plans and lab validation procedures for first silicon
• Work with software on drivers, firmware and demo workloads

What we are looking for

• BS/MS EE/CE; 7+ years in FPGA prototyping, system/board design or silicon bring-up
• Strong Vivado / Versal flow; multi-gigabit transceivers; PCIe endpoint design
• Lab skills: scopes, BERT, protocol analysers; methodical debug
• Scripting (Python/Tcl) and basic Linux driver-level literacy

Nice to have

• Rack-scale or multi-accelerator system design (GPU servers, switch systems)
• SI/PI awareness for 32G NRZ / 64G PAM4 links
• Post-silicon validation of GPU, NPU or networking ASICs

Pay: $120,000.00-$140,000.00 per year

Work Location: In person