System Debug Engineer

THE ROLE:

System debug engineer team works with different functional teams (Firmware, Silicon, Board Design, SW, etc.) to enable latest APU/CPU features and root cause the silicon/system issues. You will touch cutting edge silicon, FW, and hardware technologies. You will have chances to see how they will be implemented in our product.

THE PERSON:

A quick learner for new technologies. Excellent communication skill (both verbal and written), including Mandarin and English. Key performance skills include decision making, problem solving, teamwork.

KEY RESPONSIBILITIES:

• Study latest silicon and system features; understand new features in silicon, BIOS, firmware, SW etc., bring up new product.
• Post Silicon feature enablement and debug, especially power management and system features.
• Hands on debug issues reported by internal teams or customers, deep dive into code level to root cause the bugs.
• Lead and collaborate with silicon design, FW, SW, and other function teams to make sure issues are analyzed in time.
• Optimize the debug process with other team to improve the efficiency
• Provides detailed input into the platform definition & review of platform designs used in the silicon validation of new processors.
• Work with pre silicon teams on pre silicon feature validation and debug enablement

PREFERRED EXPERIENCE:

• Strong debugging skills. Can root cause issues from firmware, hardware, and OS. Familiar with windows debugger will be a plus.
• Solid understanding of X86 Architecture, Operating System, Driver, BIOS and FW fundamentals.
• Good understanding or hands on development/debugging experience of PCIE, USB, BIOS, Security etc. Deeply understanding PCIE/USB protocol will be a plus.
• For BIOS Domain candidate, good x86 BIOS development background and strong debug skill are required. Experience of debugging ACPI, USB enumeration, RAID etc. will be a plus.
• For OS domain candidate, familiar with windows kernel debug or Linux Kernel panic is a must; Deep understanding of Device power saving status in OS will be a plus.
• For Hardware and IO domain candidate. Better understanding of the protocol is a must.