System Debug Engineer

Date: Aug 12, 2026

Location: Bade, Taiwan, TW

Company: Super Micro Computer

Job Req ID: 27426

Job Summary:

We are looking for a Sr. System Debug Engineer to debug and to support customer and other internal deparmtnets for solving puter system issues. In this role, you will work with other departments and provide solutions for the issues and product quality improvement. The ideal candidate should be familiar with Intel low level debugging. Experience using Intel Target Probe (ITP) tool is a plus.

Essential Duties and Responsibilities:

• Diagnose the root cause of server system failures and isolate the components/failure nodes
• Interface with RD, System teams, and customer support to improve Supermicro products quality in early DVT/PVT stage
• Develop and publish test reports and communicate findings to other team members
• Using software to improve testing techniques / procedures for analyzing system failure data efficiently
• Support product technology know-how & troubleshooting skills transfer to Production from PVT to MP stage

Qualifications:

• Bachelor of Science in Electrical Engineering with minimum 3 years of working experience preferred
• Proficient in Linux and Windows OS
• Lab and debug skills are required, including experience working with and analyzing output from test equipment such as digital multi-meter and oscilloscopes, along with soldering and debugging skills
• Strong problem-solving capability
• Familiar with Intel ITP/DCI and Intel CPUs & Chipset architecture or AMD CPU/GPU & Chipset architecture is a plus

EEO Statement

Supermicro is an Equal Opportunity Employer and embraces diversity in our employee population. It is the policy of Supermicro to provide equal opportunity to all qualified applicants and employees without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, protected veteran status or special disabled veteran, marital status, pregnancy, genetic information, or any other legally protected status.