System on a Chip Architect

Wireless Communications System Architect

About The Company

We are a leading provider of high-performance, ultra-low power IP solutions across advanced CMOS nodes, enabling differentiated SoC architectures for 5G, optical networks, LiDAR, radar, automotive networking, AI acceleration, imaging, and related high-growth markets. We partner with market leaders globally and are scaling rapidly. We are seeking senior technical leadership talent to define and guide the next generation of adaptive, multi-antenna wireless platforms.

Job Description

We are seeking a Principal / Lead Wireless Communications System Architect to own the definition and architectural direction of complex wireless and multi-antenna system platforms. This individual will serve as the primary technical interface with customer system teams, lead system modeling and performance analysis, drive architectural decisions across mixed-signal and digital subsystems, and define system-level specifications that translate into silicon implementations.

This is a senior leadership role with substantial influence across product definition, roadmap direction, and customer engagement. The ideal candidate has a deep understanding of communications theory, system decomposition across analog/digital boundaries, quantization/error propagation, MIMO signal processing architectures, and end-to-end error budgeting strategies in SDR-based environments.

Key Responsibilities

Technical Leadership and Direction: Define system architecture for next-generation multi-antenna and SDR-based communication platforms, influencing product strategy and long-term roadmap planning.

Customer Technical Ownership: Lead technical engagement with strategic customers, representing system trade-offs, negotiating performance specifications, and aligning joint integration plans.

End-to-End System Modeling: Architect and maintain MATLAB and analytical models capturing the full signal chain, including channel modeling, quantization noise allocation, SNR budgeting, interplay of RF non-linearities, and DSP algorithm design constraints.

Block-Level Specification Ownership: Generate precise block-level specifications for digital baseband, calibration engines, channel processing, mixed-signal converters, and RF interfacing elements; ensure internal teams understand the architectural rationale behind these specifications.

Cross-Domain Integration: Drive alignment between digital architecture, signal processing algorithms, mixed-signal circuit selections, ADC/DAC dynamic range decisions, LO/subsystem noise considerations, and thermal/power constraints.

System Verification Alignment: Collaborate with validation and silicon bring-up teams to ensure post-silicon results trace back to modeled assumptions; define measurement-level KPIs and debug methodologies when deviations arise.

Mentorship & Team Development: Provide architectural guidance to system engineers, signal processing developers, and hardware design teams; develop reusable models, internal best practices, and system-level methodologies.

Thought Leadership: Participate in internal architecture reviews, contribute to core IP innovation strategy, and represent the company in technical engagements, standards-relevant discussions, and key customer milestones.

Qualifications

Graduate degree in Electrical Engineering, Communications Engineering, or related field; PhD strongly preferred.

12+years of experience in wireless communications system architecture for advanced SDR systems.

Demonstrated ownership of end-to-end communication signal chains, including cascaded error budgeting, quantization trade-offs, and performance modeling across RF, ADC/DAC, and DSP blocks.

Deep Expertise In

MIMO and multi-user spatial processing architectures,

Channel estimation,

SNR/phase-noise budgets and their mapping into mixed-signal design requirements

System-level modeling using MATLAB or Python,

Ability to articulate complex system decisions to both internal engineering teams and senior-level customers.

Proven leadership in defining specifications consumed by RTL design, mixed-signal design, verification, and system validation teams.

Strong customer communication skills and comfort presenting architectural trade-offs to VP- and CTO-level stakeholders.

Contact:

Uday

Mulya Technologies

muday_[email protected]

"Mining The Knowledge Community"