System Verilog/UVM Design Verification Engineer

Company Description SemiAhead is an elite engineering team focused on the functional verification of complex silicon systems, delivering services from verification planning through verification closure. The company’s core mission is to help clients achieve secure, on-time tape-out while strengthening their design and verification capabilities. SemiAhead has contributed to more than 20 projects for over 10 clients across 5 countries and 2 continents, covering a wide range of application domains and workflows. The team works with functional verification solutions from major EDA tool vendors and maintains a vendor-independent perspective. With a portfolio spanning Video, Graphics, Audio, Automotive, and AI applications, SemiAhead offers one of the most comprehensive sources of verification expertise in the market.

Role Description As a Design Verification Engineer at SemiAhead, you will contribute to the functional verification of complex silicon designs, from test planning through verification closure. In this full-time hybrid role based in Bucharest, Romania, you will work both on-site and remotely, collaborating closely with design, verification, and architecture teams. Your day-to-day activities will include developing and maintaining verification environments, writing and executing testbenches, creating test plans, and implementing constrained-random and directed tests. You will analyze simulation and formal results, perform root-cause analysis of mismatches, and drive debugging efforts with RTL designers. You will also contribute to coverage analysis, regression setup, documentation of verification methodologies, and continuous improvement of internal flows and best practices.

Qualifications

• Strong skills in Functional Verification and Debugging of complex digital designs, including experience with simulation-based verification flows.
• Solid understanding of RTL Design concepts and experience working with hardware description languages (e.g., SystemVerilog/UVM or Specman/e, eUVM).
• Knowledge of Formal Verification techniques and tools, with the ability to complement simulation-based approaches is a plus.
• Good grasp of Computer Architecture fundamentals (e.g., pipelines, memory hierarchies, AMBA AXI/AHB buses, and peripherals).
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Experience with verification methodologies (e.g., UVM or eUVM), scripting languages (e.g., Python, Perl, or shell), and version control systems (e.g., Git).
• Strong analytical and problem-solving skills, with the ability to work both independently and collaboratively in a hybrid environment.
• Good written and spoken English skills; experience in semiconductor or ASIC/SoC projects is an advantage.