SystemC Design Engineer

We are looking for a SystemC Design Engineer with strong C++ and digital/SoC design knowledge to develop and maintain SystemC-based models for hardware/IP/SoC systems.

The ideal candidate will have hands-on experience in SystemC modeling, C++, TLM/TLM-2.0, and good understanding of hardware design concepts. Experience with Verilog/SystemVerilog and SoC/IP modeling is highly desirable.

Must Have Skills

• Strong programming experience in C++.
• Hands-on experience with SystemC.
• Good understanding of digital design / hardware / SoC concepts.
• Good problem-solving and debugging skills.

Key Responsibilities

• Develop and maintain SystemC models for IP, SoC and hardware components.
• Develop transaction-level and architectural models using SystemC/TLM.
• Develop, debug and optimize C++/SystemC models.
• Analyze model performance, functionality and accuracy.
• Collaborate with RTL, verification and architecture teams.
• Debug issues across SystemC/C++ models and hardware/RTL environments.