Technical Lead I - VLSI ML ST

Role description

Memory Layout JD Key Skills & Responsibilities SRAM bitcell and array layout, including abutment and optimization for area and performance Layout of memory peripherals such as Row/Column Decoders, Sense Amplifiers, Pre-charge, Write Drivers, Read/Write Assist, IO and Self-Timing circuits Experience with Single-Port SRAM, Dual-Port SRAM and ROM architectures Full memory macro floorplanning, block integration and critical signal routing Strong understanding of matching, symmetry, shielding and parasitic-aware layout techniques Layout optimization for area, timing, power and leakage Hands-on experience with DRC, LVS, ERC and parasitic extraction Experience with IR/EM, PERC, antenna and reliability checks is desirable Understanding of power grid design, decoupling capacitance and power sequencing Ability to support post-layout extracted simulations and optimize layout based on circuit/characterization feedback Experience with industry-standard custom layout and physical verification tools Exposure to advanced technology nodes and SRAM compiler development is preferred Experience

Skills

Block Integration, DRC, LVS, Leakage Optimization, Calibre, Floorplanning, Parasitic Extraction, SRAM

About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.