Technology Development Process Engineer (Hybrid Bonding & Advanced Packaging)

Position Summary

Lead the development and integration of advanced packaging technologies, with a focus on Hybrid Bonding solutions for Logic, Memory, and 3D heterogeneous integration applications. Responsible for process development, technology innovation, and customer-driven solutions from concept through qualification.

Key Responsibilities

• Develop and optimize end-to-end Hybrid Bonding processes, including wafer/die surface preparation, wet and dry cleaning, plasma activation, dielectric-to-dielectric bonding, Cu-Cu direct bonding, and post-bond annealing to achieve bonding yield, alignment, electrical performance, and reliability targets.
• Design and execute process characterization and DOE studies to establish process windows, understand bonding mechanisms, and improve critical metrics such as bond strength, void density, overlay accuracy, Cu oxidation control, and interface quality.
• Investigate and resolve process integration challenges related to CMP surface topography, surface chemistry, contamination control, pattern density effects, thermal budget, wafer / die warpage, and bonding defectivity through data-driven root cause analysis.
• Collaborate with equipment, materials, metrology, and integration teams to develop scalable solutions for die-to-wafer (D2W) Hybrid Bonding applications supporting HBM, Logic, and 3D heterogeneous integration technologies.
• Define and implement characterization methodologies using optical inspection, IR imaging, SEM, AFM, XPS, contact angle measurement, electrical test, and reliability evaluation to monitor process performance and qualify new technologies.
• Support development of advanced packaging technologies including HBM, Logic, TSV, RDL, and die-to-wafer bonding.
• Engage customers, research institutes, and ecosystem partners on joint technology development projects.
• Generate technical reports, patents, publications, and technology roadmaps.

Qualifications

• Bachelor's, Master's, or PhD in Engineering, Materials Science, Physics, or related disciplines.

• Minimum 5 years of semiconductor experience in technology development, process integration, or advanced packaging.

• Hands-on experience in one or more of the following:

  • Advanced Packaging
  • Hybrid Bonding
  • CMP
  • Plasma Processing
  • Wet Cleaning
  • TSV Integration
  • Process Integration

Preferred Skills

• Strong understanding of Hybrid Bonding mechanisms and package integration flows.
• Experience with DOE, JMP/Minitab, and statistical process analysis.
• Knowledge of reliability, failure analysis, and advanced metrology techniques.

Work Location

• Science Park II (Moving to Tampines office starting Apr 2027)