What the Master Thesis is about/background to the problem to investigate

Modern machine vision systems continuously increase in resolution and frame rate, creating demanding requirements on data transfer performance between cameras, processing units, and host computers. While GigE Vision is widely adopted in industrial vision applications, emerging technologies such as RDMA over Converged Ethernet (RoCEv2), USB4, and Thunderbolt offer new opportunities for achieving higher throughput and lower latency with reduced CPU overhead. This thesis aims to investigate and compare state-of-the-art high-speed communication technologies suitable for future machine vision products, with particular focus on FPGA-based implementations and RDMA technologies.

Thesis outline

• Literature study of GigE Vision, RoCEv2, USB4, Thunderbolt, and other high-speed interconnect technologies.
• Evaluation and benchmarking of existing RoCEv2 FPGA implementations from research groups or commercial providers.
• Performance measurements including throughput, latency, CPU utilization, memory bandwidth, and scalability.
• Investigation of FPGA implementation aspects including protocol complexity, memory architecture, hardware/software partitioning, and resource requirements.
• Development and evaluation of selected FPGA building blocks or proof-of-concept functionality related to RDMA-based image streaming.
• Estimation of feasibility, engineering effort, FPGA resource usage, and performance benefits of an in-house RoCEv2 implementation for future machine vision products.

The master thesis work focuses on the following/example of research questions

The thesis will be carried out at SICK in Linköping. You will work in a team developing next-generation machine vision solutions and gain hands-on experience with advanced networking technologies, FPGA platforms, Linux-based embedded systems, and high-performance data acquisition architectures.

Keywords

FPGA, RDMA, RoCEv2, GigE Vision, High-Speed Networking, Zynq UltraScale+, Embedded Linux, Hardware Acceleration, Ethernet, Machine Vision.

Prerequisites

• Excellent programming skills in C/C++.
• Experience with FPGA development and digital design using Verilog, VHDL, or HLS.
• Good knowledge of Linux environments, including performance analysis, driver interaction, and system-level debugging.
• Strong understanding of computer networking fundamentals, including Ethernet, TCP/IP, and packet-based communication.
• Experience working with embedded systems and System-on-Chip (SoC) platforms.

Meriting experience:

• Xilinx Zynq UltraScale+ platforms

• Vivado and Vitis development tools

• High-speed interfaces such as PCIe, Ethernet, USB4, or Thunderbolt

• RDMA technologies including RoCEv2

• Networking analysis tools such as Wireshark and iperf

Contact

For more information about the position, contact:

Fredrik Claesson, [email protected]

We warmly welcome your application — please submit it no later than October 25th.

SICK is a world-leading supplier of sensors and sensor solutions for industrial applications. We’re part of SICK AG — a global leader in sensor technology with 10,000 employees across 50 countries and headquarters in Freiburg, Germany. Together, we build technology that makes industries more efficient, intelligent, and safe.

As a Machine Vision Innovation Center, SICK Linköping develops advanced AI-powered software that drives the future of both manufacturing and logistics automation. Whether it’s helping robots pick the right item or enabling high-precision quality control with 2D and 3D vision, our solutions bring clarity, speed, and smart decision-making to complex industrial environments — all driven by a dedicated team of 100 colleagues.

We are very proud of being a healthy and attractive workplace. We have consistently been recognized as one of the best workplaces in Sweden according to the Great Place to Work survey. We actively work to reduce our climate footprint and engage in various initiatives to contribute to society and enhance diversity at our workplace.