模拟设计主管/经理(TIA）

该职位来源于猎聘 模拟设计主管/经理(TIA 跨阻放大器） 关键要求：电子工程硕士，7年以上TIA模拟电路设计，有chip leader或团队管理经验 Job Responsibilities:

• Design, analyze, and implement high-performance (＞10GHz) PLL, wireline amplifiers, CDR, SERDES, PLL, PAM4, TDCs, ToF, low-noise amplifiers, transmitters, power-amplifiers and power-drivers, or other baseband circuits like LDO, temp sensor, ADC, Filters, etc.
• The design of high-frequency (multi-gigahertz) and high-precision clocking and analog circuits.
• Use EDA tools (Cadence, Mentor) to run simulation and function verification.
• Guide layout engineer to optimize layout.
• Chip debug and testing individually and with the team.
• Other tasks assigned by line manager. Qualifications:
• MSEE in analog IC design with no less than 10 years experience.
• Experience in Cadence EDA tools.
• Team player with good communication skills.
• Experience with multi-gigahertz SERDES transmitter/receiver, TIA, PLL, CDR, LNA etc. is highly preferred.
• Desired: Knowledge of advanced circuits such as PLLs, ADCs, DACs, LNAs, drivers, NF, S-parameters, BW extension, impedance matching.
• Desired: Experience in SerDes/PLL circuit design, testing, and post-silicon bring-up and evaluation.