US_East | Product / System & PLM Engineer_L2

Possible 3 Month CTH | No Fees | Do Not Re-Post | Confidential

Submit candidates under their legal name and use only *** template.

Role name: Senior Enginner - AMD Versal / PL Integration & IPC (iRDK)

Work Location: Palo Alto, CA 94304

Start date: Immediate availability.

Background check MANDATORY

Request ID: MSTOUQ

Role and responsibilities:

Drive AMD Versal SoC bringup for the iRDK platform, with a focus on programmable logic (PL) integration and inter-processor communication (IPC) with the AMD APU.

Responsabilities:

• Bring up AMD Versal SoC on iRDK custom board from EVK reference
• Develop and validate PL integration: IP instantiation, configuration, AXI interfaces
• Implement and validate IPC mechanisms between Versal AI Core / RPU and AMD APU (RPMsg, OpenAMP, shared memory)
• Develop BSP and drivers for Versal PS subsystems (RPU and APU partitions)

Please add the below to the comment section:

Legal Name:

Current Location: (City, State & Zip Code):

Home location:

Relocate:

Bill Rate:

CTH After 3 Months:

Travelling Availability:

Availability to Start:

Phone/Mobile Number:

Email Address:

Visa Type:

Visa Expiration Date:

Hiring Status:

Are you working directly with the contractor’s visa holder:

If not indicate # of layers and names of the company:

Indicate if the Candidate has worked in CG before and where:

Ex-*** Employee:

LinkedIn Account: (If available)

Time slots for an interview:

Contractor approved to share its resume to client:

Skills summary:

Resumes will be rejected for the following reasons:

• Different format
• Missing details in comments section
• Missing text box in the header
• Photo ID included containing personal information other than legal name and photo

Fernanda González

External Resource Manager (ERM) | SubCo Staffing Center

• North America | Guatemala