Verification Engineer

• Key Responsibilities:

1. Build complex UVM/SystemVerilog testbench components and architectures.
2. Drive functional and code coverage closure to ensure design robustness.
3. Collaborate with design teams to debug complex architectural and micro-architectural issues.

Key Requirements & Skills:

• Languages & Methodologies: Proficiency in SystemVerilog and UVM (Universal Verification Methodology).
• Verification Expertise: Experience in testbench development, constrained-random verification, functional coverage, and code coverage.
• Debugging: Strong waveform debugging skills and familiarity with industry-standard simulators (Synopsys, Cadence, or Mentor Graphics).
• Domain Knowledge: Understanding of SoC/IP protocols (e.g., AMBA AXI/AHB/APB, PCIe, DDR, etc.) is a strong plus.