Verification Engineer

Project description

This is a great opportunity to work as part of a highly regarded team to deliver leading-edge solutions.

Responsibilities

Tests the Xilinx Vivado FPGA implementation flow itself

placer, routing, static timing analysis

and analyses quality of results. EDA tool QA for an FPGA engineer, not ASIC verification.

Skills

Must have

Xilinx Vivado, specifically the implementation flow

FPGA design flow

static timing analysis and design constraints

digital / logic design

debug skills

2-4 years of experience

Experience: Minimum 2, maximum 4 years.

Nice to have

EDA company experience

scripting / automation (Tcl, Python)

AI tool usage

Other

Languages

English: B2 Upper Intermediate

Seniority

Junior

Hyderabad, India

Req. VR-125501

Manual Testing

Automotive Industry

12/10/2026

Req. VR-125501