Verification Engineer

Job highlights

• Experience in UVM verification and UVM environment development (must have) . Proficient in test plan definition and testcase development in C / Assembly/System Verilog Expertise

• You should have prior knowledge and experience with UVM verification and UVM environment development

• Additional responsibilities include:

• Help develop test plan definition and development

• Micro-architecture design verification, RTL verification, and documentation

• Top-level and block-level performance verification, power, and use-case verification; and

• Support test program development, chip validation, and chip life until production maturity.

• Team Management and Building

• Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.

• Qualifications :

• Experience in UVM verification and UVM environment development (must have)

• Proficient in test plan definition and testcase development in C/Assembly/System Verilog Expertise