Virtual Prototype Engineer (SystemC/TLM) - REQ_3003

Role: Virtual Prototype Engineer Areas Of Responsibility

• Create Virtual Development Kits (VDKs) using Synopsys Virtualizer and Synopsys IP models.
• Integrate CPU, GPU, PCIe, UCIe, DDR, and peripheral IP models into a cohesive virtual platform.
• Develop SystemC/TLM ‑ 2.0 models for custom IP blocks, peripherals, and SoC components.
• Build and maintain virtual prototypes for pre ‑ silicon software development and SoC bring ‑ up.
• Develop scripts and automation for VDK assembly, configuration, and validation.
• Work closely with hardware design teams to interpret RTL specifications and convert them into SystemC/TLM models.
• Validate functional correctness of models through directed tests, regressions, and co ‑ simulation with RTL. Support firmware, driver, and OS teams using the VDK for early bring ‑ up and debugging.
• Optimize model performance, timing accuracy, and simulation speed.
• Document model behavior, APIs, and integration guidelines for internal and external teams.

Experience

• 5+ years of experience in virtual prototyping, SystemC/TLM ‑ 2.0 modeling, or pre ‑ silicon software enablement.
• Hands ‑ on experience with Synopsys Virtualizer, Platform Architect, or similar virtual prototyping tools.
• Strong proficiency in SystemC, C++, and TLM ‑ 2.0 transaction ‑ level modeling. Experience integrating Synopsys IP models (ARC, PCIe, USB, DDR, GPU, etc.) into VDKs.
• Understanding of SoC architecture: buses, interconnects, interrupts, memory maps, and clock/reset domains.
• Familiarity with embedded software bring ‑ up (bootloaders, drivers, OS kernels).
• Experience debugging complex interactions between models, firmware, and drivers. Nice to have:
• Experience with Synopsys VDK, QEMU, Simics, or other virtual platforms Exposure to RTL (Verilog/VHDL) and co ‑ simulation flows Knowledge of PCIe, UCIe, CXL, or other high ‑ speed interconnects Python/Perl scripting for automation