Young Minds Technology Solutions Pvt Ltd
VLSI Backend Developer
1 month ago
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Important information
Contract type:
Permanent
Location:
Andhra Pradesh, India
Work mode:
Onsite
Published on:
22 September 2026
What they need
VLSI Backend Developer
Experience: 0–1 Year | Fresher’s with strong academic knowledge and relevant VLSI projects are encouraged to apply
Description
We are seeking a motivated and enthusiastic VLSI Backend / Custom IC Design Engineer to join our semiconductor design team. The candidate will contribute to the design, simulation, analysis, and layout implementation of analog, digital, and mixed-signal CMOS circuits.
The role involves hands-on work with Cadence Virtuoso, Tanner EDA, and SPICE-based simulation tools for schematic design, circuit simulation, transistor-level analysis, performance evaluation, and physical layout. The candidate should have a strong understanding of CMOS fundamentals, MOSFET operation, digital and analog circuit design, VLSI design methodologies, and IC layout concepts.
Candidates should demonstrate practical knowledge of transistor-level circuit design and be able to analyze important design parameters such as power consumption, propagation delay, operating frequency, gain, noise, area, and other circuit-specific performance metrics.
Freshers with strong academic projects, internships, simulation experience, or hands-on experience in Cadence Virtuoso, Tanner EDA, SPICE, CMOS circuit design, and VLSI layout are encouraged to apply.
Required Skills
- Strong knowledge of CMOS and VLSI fundamentals
- Good understanding of MOSFET operation, CMOS inverter, transistor sizing, and CMOS logic
- Knowledge of NMOS, PMOS, CMOS logic, pass-transistor logic, and low-power CMOS techniques
- Understanding of schematic design, transistor-level circuit design, and circuit simulation Hands-on knowledge of SPICE-based circuit simulation
- Understanding of DC, AC, transient, frequency, power, delay, and parametric analyses
- Knowledge of pre-layout and post-layout simulation concepts
- Knowledge of Design Rule Check (DRC), Layout Versus Schematic (LVS), and parasitic extraction concepts
- Good understanding of digital VLSI circuits such as adders, multipliers, registers, and memory circuits
- Knowledge of analog and mixed-signal circuits such as amplifiers, OTAs, ADCs, PLLs, and related building blocks
- Good debugging, analytical, and problem-solving skills
Required Tool Knowledge
- Cadence Virtuoso
- Tanner EDA
- SPICE / HSPICE / NGSPICE or equivalent SPICE simulator
- Basic knowledge of Spectre is an added advantage
- Experience with schematic capture, simulation, waveform analysis, and layout tools
You Need to Work On
- Designing CMOS circuits at the transistor level
- Creating and analyzing circuit schematics using Cadence Virtuoso and Tanner EDA
- Performing circuit simulations using SPICE-based simulators
- Conducting transient, DC, AC, frequency, power, and delay analyses
- Designing and analyzing adders, multipliers, SRAM, PLL, ADC, OTA, op-amp, and amplifier circuits. Performing transistor sizing and circuit optimization
- Measuring power consumption, propagation delay, frequency, gain, area, and other relevant performance parameters
- Developing CMOS layouts based on schematic designs
- Performing DRC and LVS verification
- Conducting pre-layout and post-layout simulations
- Supporting research and development activities in CMOS VLSI design
- Continuously learning emerging CMOS, FinFET, and advanced semiconductor technologies
Qualification
- B.Tech / B.E. in Electronics and Communication Engineering (ECE)
- Experience: 0–1 Year
- Freshers are eligible to apply
- Candidates with strong knowledge of CMOS, VLSI, analog/digital circuit design, and SPICE simulation are preferred
- Candidates with academic projects or internships involving Cadence Virtuoso, Tanner EDA, SPICE, CMOS circuits, or VLSI ayout are strongly preferred
What Matters Most
We are looking for candidates with strong fundamentals in CMOS and VLSI design, practical interest in transistor-level circuit design, and a willingness to learn professional IC design methodologies.
The ideal candidate should be comfortable working with Cadence Virtuoso, Tanner EDA, and SPICE simulation environments and should have an interest in designing and analyzing circuits such as adders, multipliers, SRAMs, PLLs, ADCs, OTAs, operational amplifiers, and CMOS amplifiers.
Strong analytical skills, circuit-debugging ability, attention to design quality, and hands-on project experience are highly valued. Freshers with relevant CMOS/VLSI projects and practical simulation or layout experience are strongly encouraged to apply.
How to Apply:
Interested candidates are encouraged to send their resumes to [email protected] or contact at 8688400273. Please include "Job Role" in the subject line.
Pay: From ₹180,000.00 per year
Benefits:
- Paid time off
- Provident Fund
Work Location: In person
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