Design Testability Engineer

Mandatory Skills:

• DFT
• Cadence Modus
• Cadence Genus
• VLSI / ASIC / SoC
• DFT Implementation
• Scan Insertion / ATPG / DFT Validation

Roles & Responsibilities:

• Perform DFT implementation and validation for ASIC/SoC designs.
• Work on scan insertion, ATPG, DFT checks and coverage improvement.
• Use Cadence Modus and Genus for DFT-related activities.
• Debug DFT issues and support design verification.
• Collaborate with RTL, Physical Design and Verification teams.