Physical Verification Engineer

Job highlights

• . Should be proficient in DRC and LVS analysis at advanced nodes like 5nm or below

• Prior work experience on FullChip RDL like IO / PADRing routing will be preferred

• . Understanding multi voltage regions will be preferred

• Scripting will be preferred

• . RDL experience . Full chip/ subsystem LV experience in layout debug and fix . Good PV-PD knowledge . .

• Work with floorplan and physical design engineers to drive physical verification convergence.

• Should be proficient in DRC and LVS analysis at advanced nodes like 5nm or below.

• Good knowledge in specific areas like Antenna, ESD, ERC, LUP will be preferred.

• Working knowledge on full chip phyV will be added advantage.

• Prior work experience on FullChip RDL like IO/PADRing routing will be preferred.

• Understanding multi voltage regions will be preferred.

Tools:

• Expertise in Calibre/ICV and ICC2 tools.

• Scripting will be preferred.

• Scripting inside Calibre tool will be added asset.

• Automation [tcl, perl, python, etc,..]

• RDL experience

• Full chip/ subsystem LV experience in layout debug and fix

• Good PV-PD knowledge