Verification Engineer (SystemVerilog / UVM)

Job highlights

• Good understanding of PCIe and CXL protocols is an added advantage

Location : Bangalore / Chennai

Mandatory Skills :
Understanding Specs and Standards and developing relevant test plans
Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase
the rate with which bugs are found and resolved
Thorough understanding of Digital design concepts
Thorough understanding dv methodologies and tools
Good understanding of PCIe and CXL protocols is an added advantage
Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite/CHI