Package Mechanical FEA Engineer

CScale is building the interconnect for gigawatt-scale AI. As AI scale-up moves toward deployments spanning thousands of accelerators and dozens of racks, the network needs to deliver high bandwidth, predictable low latency, and continuous communication. CScale is building integrated optical interconnect designed for this new scale, enabling accelerators to work together like a single, much larger computer. But at this scale, performance is only part of the challenge. Optical failures are inevitable, and the system needs to keep running. CScale is designing the interconnect for continuity. Lasers will fail. Compute shouldn’t. The ambition is simple: Build AI interconnect you can take for granted. CScale came out of stealth in September 2026 with $145 million in Series C funding, bringing total funding to $188 million.

The Role This position owns structural finite element analysis for CspeedIO optical engine packages: warpage prediction through the assembly process, stress in bump and interconnect structures, and the lifetime models supporting qualification.

Responsibilities Warpage and process simulation

• Predict warpage at each stage of the assembly process — bonding, reflow, underfill cure, encapsulation, lid attach, singulation
• Own the flatness, coplanarity, and facet planarity budgets that assembly and optical coupling depend on.

Interconnect stress and reliability

• Analyze stress and strain in micro-bump, copper pillar, C4, and second-level interconnect structures, including chip-package interaction and low-k dielectric risk.
• Own solder and interconnect fatigue life prediction, and model thermal cycling, shock, drop, and board-level reliability against JEDEC and IPC methodology.
• Quantify stress in the photonic IC and its consequences for optical performance, in partnership with the photonic design team.

Methodology, correlation, and design influence

• Define simulation methodology and modeling standards with documented, auditable assumptions, and correlate predictions against measured warpage, cross-section, and reliability data.
• Provide design guidance and sign-off criteria during architecture definition — stack-up, thickness, bump pitch, underfill and stiffener selection — rather than after design freeze.
• Engage substrate suppliers and OSATs on process assumptions, measured warpage data, and material characterization.

Required Qualifications

• MS or PhD in Mechanical Engineering, Materials Science, Engineering Mechanics, or equivalent practical background.
• 6+ years of structural FEA for semiconductor packaging, including warpage and interconnect stress analysis on a product carried into build.
• Deep hands-on capability in Ansys Mechanical, Abaqus, or equivalent, including nonlinear material modeling.
• Command of nonlinear and time-dependent material behavior — creep, viscoplasticity, viscoelasticity, fatigue — with correct treatment of temperature and rate dependence.
• Working knowledge of solder constitutive models and fatigue life prediction methods.
• Demonstrated correlation against physical measurement, and the judgment to distinguish a modeling error from a process excursion.

Preferred Qualifications

• Chip-package interaction analysis including back-end-of-line and low-k dielectric stress.
• Board-level reliability and PCB-to-package interaction modeling; JEDEC and IPC qualification methodology.
• Photonic or optoelectronic packaging, particularly warpage as an optical alignment constraint or stress effects on optical behavior.
• Coupled thermal-structural workflows, including transfer of a computed temperature field into a structural model.
• Design of experiments and surrogate modeling to compress large parametric studies.