Cpu Integration & Physical Verification Engineer

General Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

As CPU Integration CAD engineer, you will enable the floor-planning, physical design (PD), physical design verification (PDV), and signoff of Qualcomms class-leading Oryon CPU cores.

Qualifications

• 6+ years of hands-on experience in development of high-performance chips - either in a design or CAD role
• High level of programming proficiency (Python and Tcl). Knowledge of data structures and algorithms
• Experience with automation
• Experience with a broad variety of Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV
• Experience with advanced technology nodes (5nm or lower)
• Strong user of industry-standard PDV tools such as Siemens/Mentor Calibre
• Strong user of industry-standard place-and-route tools such as Cadence Innovus
• Proven track record of managing and regressing place-and-route flows