Noc Design Verification Staff Engineer

Company: Qualcomm India Private Limited

Job Area: Engineering Group, Engineering Group > Hardware Engineering

Job Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what''s possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Looking for an experience Verification Architect/ Engineer, who will be responsible for verification of next generation Infrastructure IPs (DDRSS, Memory Controllers etc.)which goes into System-on-chip (SoC) for smartphones, tablets and other product categories. In this position you will be expected to plan and implement IP/Cluster/Formal verification flows for the Infra IPs. Also expected to coordinate with different Design and SOC teams throughout the IP development cycle.

Responsibilities

• Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage)
• Develop test plan and test cases to cover design feature set, follow up with stakeholders on code coverage, functional coverage closure at different levels of test bench
• Work closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure
• Debug of regression signatures and identifying bug fixes
• Responsible for Quality sign off and required documentation
• Developing/Deploying scripts/tools for validation (Certitude, VC Formal, VPlan)
• Debug and root cause post silicon issues in collaboration with Design, SW and test teams
• Work with SoC level performance modeling team on latency, bandwidth analysis next-generation experiences and drives digital transformation to help create a smarter, connected future for all.

Required Skills

• Strong debugging, Analytical and problem-solving skills
• UVM based verification
• ARM bus protocols
• Virtual Memory concepts
• SoC system architecture
• Monitors
• Scoreboards
• Sequencers
• System Verilog
• Dynamic clock gating

Desired Skills

• Automotive Safety Integrity Levels (ASIL)
• Python or Perl for Automation initiatives
• C/C++/SystemC for performance models
• Post-si bring-up and HW-SW debug experience would be an added advantage

Qualifications

• Bachelor/Masters Degree in Electronics Communication / Micro Electronics
• 8 Years of Experience in IP verification or related
• Experience with UVM and ARM Bus protocols.